It’s very sweet. Gonna through DrunkenSlug in as well. I’ve used geek, eweka, slug, and abnzb. I currently use geek and slug. Eweka is also great, just didn’t re-up. Abnzb is meh.
It’s very sweet. Gonna through DrunkenSlug in as well. I’ve used geek, eweka, slug, and abnzb. I currently use geek and slug. Eweka is also great, just didn’t re-up. Abnzb is meh.
Tbf, I am not a grey beard chief engineer, and I strongly prefer VHDL for design. For verification I actually really like SystemVerilog.
VHDL is strongly types, which prevents a lot of issues with types that I’ve hit with [System]Verilog.
Also, having learned VHDL first, I think it is easier to go from VHDL to Verilog, as opposed to vice versa. And this is mainly because VHDL is stricter.
Lol, so much of the FPGA industry 🤣. Especially East coast of the US
Same here.
VHDL represent. Although it’s arguably not a “programming language”
Define “a minute”. I normally get things from Usenet within minutes of it finishing airing